January 11, 2018

ASIC Design

RTL Design:

VentureSoftGlobal design team has strong experience in understanding the product/marketing requirements and defining the product specifications

  • Microarchitecture definition
  • IP integration (Mixed Signal, High Speed Serial interfaces DDR, PCIe, USB, Ethernet

Design Verification (Block and Full Chip):

VentureSoftGlobal Verification team has expertise in building large-scale complex verification environments using C/C++, System C, System Verilog, UVM/OVM/VMM methods. Our verification team has developed Productivity tools, Quality checks and methodologies to aid smart debugging for a faster ASIC development. The functional coverage metrics are continuously measured throughout the verification cycle

  • Testcase and Testplan development
  • Assertion Based Verification (ABV)
  • Coverage driven Verification (CDV)
  • Constraints based Random Verification
  • Reference based Verification
  • Formal Verification at various stages

Design For Testability (DFT):

VentureSoftGlobal  ASIC test development team has expertise in   providing coverage driven offerings  for

  • Scan Insertion
  • Logic BIST
  • Memory BIST
  • ATPG vector generation
  • Boundary Scan Insertion

Physical Design (Netlist to GDSII Implementation)

VentureSoftGlobal Physical design team has extensive experience in designing highly complex ASICs for High speed and Low power designs.  Our team was involved in all areas of physical implementation of designs ranging from 1 million to 50 million in various technology nodes from 130nm to 7nm. The team has experience with all the standard industry tools, vendors and flows

  • Synthesis
  • Floorplanning
  • Timing Analysis/Closure (STA)
  • Place and Route
  • Power Analysis
  • Physical Verification (LVS, DRC, ERC, DFM)
  • Tapeout Signoff

Foundation IP

VentureSoftGlobal Library development team has experience in developing the  Standard Cell and memories for Foundation IP (Ultra Low Power) especially for applications such as IoT and consumer devices where the energy  efficiency is paramount.

  • Standard Cell layout
  • Memory layout
  • Analog layout
  • Physical Design Kit (PDK) development
  • Technology File development